1. Field of the Invention
The invention generally relates to integrated circuit testing.
2. Description of the Related Art
FIG. 1 illustrates a prior art integrated circuit 101 on a wafer 100. Integrated circuit 101 comprises a band gap reference (BGR) voltage generator 110, a switch 112, a supply and control voltage generator 140, memory control circuitry and one or more memory arrays 150, control circuitry 130, test circuitry 160, and adjustment circuitry 170.
BGR voltage generator 110 generates a substantially temperature independent BGR voltage from which supply and control voltage generator 140 generates supply and control voltages for memory control circuitry and memory array(s) 150. Because the BGR voltage generated by BGR voltage generator 110 may vary from its desired target value due to, for example, manufacturing tolerances, a tester 180 is used to test integrated circuit 101 using an externally forced BGR voltage. This externally forced BGR voltage may be varied over a range that includes the range of variations expected in the BGR voltage produced by the generator 110. By testing the integrated circuit device over this range (e.g., by writing and reading known test data patterns to the memory array(s) 150, some assurance may be gained that the integrated circuit 101 will operate properly over the expected range of voltages produced internally by the generator 110.
Tester 180 tests integrated circuit 101 in accordance with a flow diagram 200 of FIG. 2. Tester 180 for block 202 supplies a supply voltage VDD through an external VDD pad 103 and supplies a ground supply voltage VSS through an external VSS pad 104 to power integrated circuit 101. Tester 180 for block 204 supplies control signals to control circuitry 130 through one or more external control pads, such as pads 106 and 107 for example, to place integrated circuit 101 in a test mode in which control circuitry 130 activates switch 112 to couple an external VBGR pad 109 to BGR voltage generator 110. Tester 180 for block 206 then forces a BGR voltage substantially at a desired target value onto integrated circuit 101 through external VBGR pad 109 and for block 208 tests integrated circuit 101 using the externally forced BGR voltage.
Tester 180 controls control circuitry 130 to control test circuitry 160 to test memory control circuitry and memory array(s) 150 using the externally forced BGR voltage, for example, as known data patterns are written to the arrays 150 and read back to verify operation of the integrated circuit 101 at the forced BGR voltage. In some cases, the BGR voltage generator 110 may be adjusted (during or after additional testing) by adjustment circuitry 170 to trim the internally generated BGR voltage (e.g., by setting of one or more fuses).
In testing integrated circuits on a wafer, it is generally desirable to have a high degree of parallelism, that is the use of the same tester resources for multiple integrated circuits on the wafer. The number of tester channels that have to be connected to each integrated circuit under test, however, limits the degree of parallelism that can be achieved. Unfortunately, the need to supply an externally forced BGR voltage requires a separate tester channel for each integrated circuit under test.